Graduation Semester and Year
2021
Language
English
Document Type
Dissertation
Degree Name
Doctor of Philosophy in Materials Science and Engineering
Department
Materials Science and Engineering
First Advisor
Choong-Un Kim
Abstract
As the shrinkage of electronic devices becomes more appealing, so do their high capacity and efficiency. This demand for ever-shrinking sizes of electronic devices follows the trend predicted by Moore’s Law. To achieve smaller devices, reduced sizes of solder joints, Cu traces, Cu pads, and other components in packages are implemented with tighter tolerances for geometries and layouts. With each incremental change in dimension or material, new reliability challenges emerge. Electromigration (EM), the directional diffusion of atoms with the flow of electrons, has been an inevitable reliability concern for microelectronic device packaging. It is one common failure mechanism in wafer-level chip scale packages (WCSP). EM is heavily influenced by the presence of current crowding, resistance, and subsequent Joule heating (JH). As the current flows through an integrated circuit (IC), the electrons flow in the opposite direction, causing a mass diffusion of metal atoms from the cathode end of a solder joint to the anode end of a solder joint either by dissolution at the interface or by migration within the bulk. As this directional EM diffusion occurs, vacancies in the conductive material lattice begin to form. In classical EM failure, these voids propagate until they reach across the entire solder cathode interface, and EM failure finally occurs by open circuit. Failure by EM is especially exacerbated by the demand for ever-decreasing device sizes and increased efficiency and power carrying capabilities. Appealing to these demands requires smaller IC vias and increased densities of current paths, leading to larger current densities as high current flows through thin IC components. There are a number of methods employed by industry to mitigate the effects of EM, including the implementation of an under-bump metallization (UBM) layer, solder shape and size, and diffusion barriers. A UBM is essentially a layer of Cu that is situated between the Cu trace on the silicon chip substrate and the solder joint mounted onto the printed circuit board (PCB), through which current is routed to the solder joint, to the UBM and the redistribution layer (RDL), and finally, to the chip. Another mitigation effort is the implementation of a polyimide (PI) layer situated between the RDL and the UBM with limited sized openings to control the current crowding at the UBM/SAC interface. The following studies aim to understand the effects of such design modifications’ effects and in-use conditions on theoretical mechanisms behind the EM failure in device ICs, paying close attention to current crowding, JH, and localized stress on the cathode end of the device under test (DUT) solder bump, where EM voiding occurs. The research presented in this dissertation is intended to explore the fundamental reasoning behind EM experimental results reported by Yi Ram Kim et. al. [1-3] through the finite element method (FEM) with four key objectives: 1) Identify the fundamentals supporting whether a certain current flow configuration may be more favorable over another in early or later failure; 2) Determine the fundamentals supporting the hypothesis that there is an optimal UBM thickness that can extend the lifetime of a DUT in an IC; 3) Determine the fundamental mechanisms behind how the duty factor (DF) of direct current (DC) “on time” may accelerate or decelerate the failure rate in DUTs incorporated in WCSPs; 4) Investigate how the alteration of a PI opening impacts the current crowding and stress in the DUTs incorporated in WCSPs. This dissertation presents key findings in our studies, especially those which lead to a better understanding of metallurgical and structural mechanisms affecting EM failures. Compressive stress has been found to benefit the WCSP interconnect reliability against EM mechanisms as it blocks the void growth across the interface between a SAC solder joint and a UBM. However, those have been determined to be limited by the current crowding and JH. Interconnect designs and parameters were further investigated through FEM to identify those which best benefit WCSPs against EM failure, such as UBM thickness and controlled PI openings. Supporting for ideal current conditions such as symmetry DC, asymmetry DC, and pulsed-DC under low and high-frequencies was also furnished. Future work, including an investigation of plasticity effects under non-DC conditions and comparing different solder joint geometrical parameters, are also suggested in this dissertation.
Keywords
Wafer-level chip scale packages, Electromigration, Finite element method, Semiconductors, Reliability, Solder joints
Disciplines
Engineering | Materials Science and Engineering
License
This work is licensed under a Creative Commons Attribution-NonCommercial-Share Alike 4.0 International License.
Recommended Citation
Osmanson, Allison Theresa, "Study of SAC Solder Interconnect Parameters in Microelectronic Semiconductor Packaging and their Effects on Electromigration Failure Mechanisms" (2021). Material Science and Engineering Dissertations. 108.
https://mavmatrix.uta.edu/materialscieng_dissertations/108
Comments
Degree granted by The University of Texas at Arlington