Graduation Semester and Year
2014
Language
English
Document Type
Thesis
Degree Name
Master of Science in Electrical Engineering
Department
Electrical Engineering
First Advisor
Alan W. Davis
Abstract
Input/Output (IO) circuits enable interface between logic circuitry and the actual or raw information to be processed. They also help to isolate the integrated circuit from the unsafe, unknown and noisy environment. IOs come in many flavors and the General Purpose IO (GPIO) is one among them. GPIOs can operate as an input, output or a bi-directional circuit. The purpose of this work is to design an area optimized industrial quality bi-directional GPIO with separate enable signal for transmitter and receiver which can drive a current of at least 16 mA into the PAD (the circuit point where the capacitive load is connected). The typical IO power level (the power at which a Printed Circuit Board, PCB operates) is 1.8 V and the core (the logic circuitry) power level is 1.0 V. Drive strength control and slew rate control are included in the GPIO implementation. Since many GPIOs could be placed in an IO ring (IOs placed around the periphery of the chip), its placement optimization is important for optimal chip area, as well as, robust IO ring from performance and qualification requirements. IOs need to be protected from ESD events. One of the key ESD protection methodologies involve accurate ESD device sizing versus ESD current path distance optimization. A calculator is developed to predict the optimum distance at which a power clamp should be present for a given IO ESD device size and overall current carrying element availability. This tool is supposed to get certain inputs regarding the ESD protection devices from the user and suggest an optimum distance at which a power clamp should be placed in an IO ring. This work is intended to produce one of the most compact GPIOs in the given technology node (the distance between source and drain of the CMOS transistor), 28 nm and a clamp placement calculator which works for different technology nodes.
Disciplines
Electrical and Computer Engineering | Engineering
License
This work is licensed under a Creative Commons Attribution-NonCommercial-Share Alike 4.0 International License.
Recommended Citation
Abraham, Shiju, "GPIO Design, Layout, Simulation And ESD Clamp Placement Calculator" (2014). Electrical Engineering Theses. 167.
https://mavmatrix.uta.edu/electricaleng_theses/167
Comments
Degree granted by The University of Texas at Arlington