Fahad Mirza

Graduation Semester and Year

2014

Language

English

Document Type

Thesis

Degree Name

Master of Science in Electrical Engineering

Department

Electrical Engineering

First Advisor

Unknown

Abstract

For the last few decades, Moore's law has been driving the microelectronics industry to achieve high performance with small form-factors at a reasonable cost. The continued miniaturization of the transistors has resulted in unparalleled growth in the electronics industry. Further performance increment via size scaling; however, will not be costeffective and difficult to manufacture. To achieve further performance enhancement at a reasonable cost, advanced packaging is being leveraged. Advanced packaging technologies such as System-on-chip (SOCs), system-in-package (SiPs), and 3-D TSV ICs provide significant power and performance enhancement without having the need to migrate to the higher technology node. As planar device miniaturization continues to its ultimate limits, the complexity of circuit interconnections for 2-D devices becomes a limitation for performance and drives up power dissipation. 3-D technology would enable extremely dense solid-state memory to be arrayed within a few microns of the processing elements, which reduces access times. It is clear that these advanced packaging technologies are advantageous from cost and performance standpoint, and are therefore shaping up as an integral part of the mainstream consumer electronics, especially handheld applications. However, the development and sustainability of such "big things" requires immense numerical and experimental testing in order to have a reliable device. Reliability and performance of such systems holds the key. Mechanical reliability needs to be evaluated and failures need to be mitigated for smooth and effective transition to the market. There is a need to develop sophisticated and compact numerical and experimental methodologies for efficient mechanical and performance analysis. In this work, a novel compact modeling methodology has been developed to analyze the multi-level interconnects damage during process and product qualification for advanced high-end mobile application packages. The proposed technique has been rigorously validated against the full array models and literature and a correlation model to determine the modified ANAND's viscoplastic constants for the effective solder block compact model (for SAC 305) has been formulated. The proposed methodology has resulted in a significant computational time reduction during technology development leading to faster lead times.

Disciplines

Electrical and Computer Engineering | Engineering

Comments

Degree granted by The University of Texas at Arlington

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