Graduation Semester and Year
Fall 2024
Language
English
Document Type
Dissertation
Degree Name
Doctor of Philosophy in Electrical Engineering
Department
Electrical Engineering
First Advisor
Chenyun Pan
Second Advisor
Sungyong Jung
Third Advisor
Ioannis D Schizas
Abstract
Traditionally, the semiconductor logic devices and very large-scale integrated circuits implemented based on them have fixed functions after fabrication. Although some circuit systems, such as field programmable gate arrays (FPGAs), provide circuit reconfiguration for swift and flexible circuit development, the feature is not rooted in device-level reconfiguration. The function-fixed logic devices are the mainstream scheme due to their advantageous area, delay, and energy. However, this trend has experienced changes with the development of technology. In recent years, more and more reconfigurable logic gates (RLGs) have been proposed, which may improve logic circuit area efficiency by increasing the number of functions performed by a fixed number of logic gates. Advanced material technologies, such as valley spin (VS) or reconfigurable field-effect transistor (RFET), offer a variety of device choices that are aimed at providing rich or even arbitrary operators in one compact logic device. Despite all these advances, the emerging RLGs are not wildly leveraged in either reconfigurable circuits or application-specific integrated circuits (ASIC). One of the critical problems is lacking mature electronic design automation (EDA) tools.
For ASIC scenarios, most existing research efforts have focused on device-level design with the assumption that improving circuit area efficiency will motivate their wide adoption. A limited number of systematic design methods and EDA tools have been proposed to leverage RLGs in logic circuits. However, they cannot fully unleash the power of RLG-based circuits for higher area efficiency due to various drawbacks, such as sub-optimal design methodology and lack of customization of specific device technologies.
For reconfigurable circuit scenarios, a very successful application example is FPGAs, which are usually realized by logic units that are called look-up tables (LUTs). An RLG-based reconfigurable logic block, denoted as MCluster, can also be used as the basic logic unit to implement FPGA architectures. Compared to LUT which has infinite logic representation ability with a significantly redundant area, MClusters improve area by providing function-level reconfiguration based on gate-level reconfiguration. However, RLG-based logic blocks can only realize functions with limited complexity since it is consisting of several RLGs. Moreover, most LUTs are single-output, and RLG-based logic blocks usually provide multi-output functions. These differences determine that traditional FPGA EDA methods do not well support the FPGA design on an MCluster base.
The dissertation introduces several synthesis approaches for leveraging RLGs, which belong to different phases of traditional circuit synthesis design flow. In the order they appear in the regular flow, the work performed in this dissertation comprises a few different, but interrelated thrusts. In the first, a novel directed acyclic graph (DAG)-based datapath synthesis method based on graph isomorphism is discussed, in which gate reconfiguration is utilized to enable area minimization on a larger scope of circuits. The second thrust discusses a generic design methodology to achieve area-efficient reconfigurable logic circuits by using exact synthesis based on Boolean satisfiability (SAT) solver. In this thrust, a series of topology-based SAT acceleration methods are also proposed to shorten the runtime with ignorable area deterioration. In the third and final thrust, a novel FPGA technology mapping approach for multi-output LUT and MCluster is discussed.
Keywords
Reconfigurable Circuit, EDA, Synthesis, FPGA Mapping, Exact Synthesis, Datapath Synthesis
Disciplines
VLSI and Circuits, Embedded and Hardware Systems
License
This work is licensed under a Creative Commons Attribution-NonCommercial-No Derivative Works 4.0 International License.
Recommended Citation
Shang, Liuting, "Novel synthesis methods for emerging reconfigurable logic devices: exact synthesis and technology mapping" (2024). Electrical Engineering Dissertations. 403.
https://mavmatrix.uta.edu/electricaleng_dissertations/403