Graduation Semester and Year
2019
Language
English
Document Type
Dissertation
Degree Name
Doctor of Philosophy in Electrical Engineering
Department
Electrical Engineering
First Advisor
Zeynep Celik-butler
Abstract
The main objective of this work is to identify and characterize gate oxide defects that are present in submicron p-channel metal oxide semiconductor field effect transistors (pMOSFETs) and which are responsible for random telegraph signals (RTS). With the downscaling of MOSFETs, alternating capture and emission of channel carriers by defects residing at the oxide-semiconductor interface and bulk oxide have become a pronounced problem. Even though RTS has been used for several years as a tool to characterize the interface/bulk defects, RTS in pMOSFETs has been under-reported compared to that in nMOSFETs, resulting in less information on hole defects in pMOSFETs responsible for RTS. This work, using variable temperature RTS measurements on state-of-the-art pMOSFETs, provides an extensive study of the location of the active oxide defects and their energy in the oxide bandgap using a model based on first principles, and suggests a possible structure for the defects responsible for RTS. There has been a significant knowledge gap in the field of the role of hot carrier stress for hole trapping in pMOSFETs that lead to RTS. In addition, the origin of trap activation and deactivation due to stress in pMOSFETs is not completely understood yet. Obtaining information about the trap generation and passivation mechanisms and the newly generated trap structure would need extensive amount of RTS data on several pMOSFETs at both pre-stress and post-stress conditions. This work presents variable temperature RTS data on unstressed and stressed submicron pMOSFETs. A structure of the defects responsible for RTS is proposed that can be generated or passivated as a result of stress. At first room temperature RTS measurements were done on pMOSFETs of different gate areas biased at strong inversion and linear region of operation. The room temperature RTS data allowed extraction of trap position from the Si-SiO2 interface, trap energy level with respect to the SiO2 valence band edge and the trap capture cross-section. The variable temperature RTS data, on the other hand, can be used to obtain information on the trap energy parameters such as capture activation energy, change in enthalpy and entropy in the system due to carrier emission, and the trap relaxation energy. Variable temperature RTS measurements were done on the pMOSFETs varying the temperature from 295 K down to 165 K. The trap energy parameters thus obtained were compared to the already published trap parameters reported by several researchers using other techniques. A possible trap structure was suggested. Channel hot carrier (CHC) stress was applied to different sized pMOSFETs at room temperature for different durations. RTS measurements were performed following each stress step. Comparing the trap capture cross-sections and trap energy levels with respect to the SiO2 valence band edge to the previously reported trap parameters, a structure of the stress-generated traps was suggested. Traps were observed to appear and disappear randomly after each stress interval. A possible explanation behind such phenomenon was proposed as well. To obtain more information about the stress-induced traps, variable temperature measurements were done on fresh and stressed pMOSFETs. The MOSFETs were stressed at room temperature, and a subsequent RTS measurement was performed at temperatures from 295 K down to 165 K. Comparison of the energy parameters of the stress-induced traps with the already characterized traps allowed us to make conclusions on the structure of those stress-induced traps. Since 1/f noise is a major concern in short channel transistors, the traps responsible for 1/f noise in these devices need to be passivated as much as possible. This will help to quantify the maximum achievable limit of flicker noise in the downscaled devices, and hence find a technique for growth of gate oxide with minimal flicker noise. In this research, voltage and current noise power spectral densities of different sized nMOSFETs in three wafers with different oxide growth conditions have been measured, normalized, and compared. Correlations of the oxide growth steps with the measured flicker noise have been investigated. The main novelty of this work lies in the facts that (i) it is the first time when such detailed analyses has been done on hole defects near the Si-SiO2 interface that are responsible for RTS. A physical structure of the defects causing the switching events has been proposed. (ii) In addition to the process-induced defects, possible structures for stress-induced defects have also been discussed. (iii) Generation, activation and deactivation of traps with stress are experimentally observed and explained. Finally, (iv) Trap volatility because of stress has been observed, and explained. Possible defect structures have been suggested, which provides further insight into the reliability issues in pMOSFETs in terms of noise and degradation.
Keywords
Random telegraph signals, MOSFETs, Flicker noise, Defects, Characterization
Disciplines
Electrical and Computer Engineering | Engineering
License
This work is licensed under a Creative Commons Attribution-NonCommercial-Share Alike 4.0 International License.
Recommended Citation
Rouf, A. S. M. Shamsur, "Identification and Characterization of Gate Oxide Defects Responsible for Low Frequency Noise in MOSFETs" (2019). Electrical Engineering Dissertations. 353.
https://mavmatrix.uta.edu/electricaleng_dissertations/353
Comments
Degree granted by The University of Texas at Arlington