Technology/Memory Co-Design and Co-Optimization Using E-Tree Interconnect

Authors

Zhenlin Pei
Mahta Mayahinia
Hsiao-Hsuan Liu
Mehdi Tahoori
Francky Catthoor
Zsolt Tokei
Chenyun Pan

Document Type

Article

Abstract

For on-chip SRAM, a major portion of delay and energy is contributed by the H-Tree interconnects. In this paper, we propose an E-Tree interconnect technology to minimize the H-Tree delay and energy overheads based on an efficient interconnect technology/memory co-design framework for nonuniform workloads. Various array- and interconnect-level design parameters are co-designed for optimal performance using three emerging interconnect materials with a realistic cell library.

Publication Date

6-5-2023

Language

English

License

This work is licensed under a Creative Commons Attribution 4.0 International License.

Recommended Citation

Pei, Zhenlin; Mayahinia, Mahta; Liu, Hsiao-Hsuan; Tahoori, Mehdi; Catthoor, Francky; Tokei, Zsolt; and Pan, Chenyun, "Technology/Memory Co-Design and Co-Optimization Using E-Tree Interconnect" (2023). Association of Computing Machinery Open Access Agreement Publications. 13.
https://mavmatrix.uta.edu/utalibraries_acmoapubs/13