Graduation Semester and Year
2017
Language
English
Document Type
Thesis
Degree Name
Master of Science in Mechanical Engineering
Department
Mechanical and Aerospace Engineering
First Advisor
Dereje Prof Agonafer
Second Advisor
Pavan Mr Rajmane
Abstract
The reliability assessment of package assembly is important to predict the performance of any microelectronic devices. Formation of fatigue cracks at the interface between the solder joint and component is the common failure occurring in widely used microelectronic devices. Lead-free solders and advanced silicon process nodes with the low-k dielectrics flip chip package are used and are facing significant reliability challenges. The mismatch of coefficient of thermal expansion (CTE) between the chip and substrate affect solder joint reliability. The underfill encapsulant packaging is widely used to improve chip device reliability. In this paper, we are studying the effect of different underfill material and gap height between the die and PCB can improve package reliability. The finite elements method (FEM) have been leveraged for this study. Thermal fatigue takes 80% failure among all the electronic components failure, here Accelerated thermal cycling(ATC) have been used as a load to test stress distribution on package assembly and plastic work in solder joints.
Keywords
CTE, FEA, QFN, Thermal Cycling, ATC
Disciplines
Aerospace Engineering | Engineering | Mechanical Engineering
License
This work is licensed under a Creative Commons Attribution-NonCommercial-Share Alike 4.0 International License.
Recommended Citation
Crisanth, Paul, "Effect of Underfill Material & Gap Height on Reliability of low-k Large-Die Flip Chip Package under thermal Loading" (2017). Mechanical and Aerospace Engineering Theses. 745.
https://mavmatrix.uta.edu/mechaerospace_theses/745
Comments
Degree granted by The University of Texas at Arlington