Hardik Parekh

Graduation Semester and Year

2013

Language

English

Document Type

Thesis

Degree Name

Master of Science in Aerospace Engineering

Department

Mechanical and Aerospace Engineering

First Advisor

Dereje Agonafer

Abstract

Semiconductor industry has recognized the need to replace traditional Al/SiO2 interconnects with Cu/Low-k interconnects in the mainstream electronics devices following the latter's impact on power, RC delay, and cross-talk reduction. However due to lower elastic modulus, strength, and poor adhesion characteristic, reliability of the Cu/Low-k interconnects turns out to be a concern for its integration in the back-end-of-line (BEoL). Flip-chip attachment process (cooling from ~200C to room) can result in critical damage in nano-scale Cu/Low-k interconnects. The objective of this study is to improve the reliability of Cu/Low-k interconnects during die attach reflow process for a specific die to substrate size ratio by varying a group of design parameters such as substrate thickness and solder bump footprint. Preliminary parametric study has shown that the variation in the concerned design variables has a significant effect on the solder bump (fBEoL) and low-k layer damage (BEoL) [1]. However, there is a trade-off between the solder bump and the dielectric damage with bump footprint, thereby arising a need to perform a multi-objective design optimization. A simulation based multi-objective design optimization has been carried out to improve BEoL/fBEoL reliability under reflow loading by minimizing the following objective functions 1) strain energy in solder bump and 2) peeling stress in dielectric (low-k layers). This work is of immense importance from process integration standpoint. It can provide a quantitative upstream guideline to the process/electrical team on the BEoL/fBEoL damage.

Disciplines

Aerospace Engineering | Engineering | Mechanical Engineering

Comments

Degree granted by The University of Texas at Arlington

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