Pavan Rajmane

ORCID Identifier(s)

0000-0003-3301-7856

Graduation Semester and Year

2018

Language

English

Document Type

Dissertation

Degree Name

Doctor of Philosophy in Mechanical Engineering

Department

Mechanical and Aerospace Engineering

First Advisor

Dereje Agonafer

Abstract

The convergence and miniaturization of computing and communications dictate building up rather than out. As planar device miniaturization continues to its ultimate limits, the complexity of circuit interconnections for 2-D devices becomes a limitation for performance and drives up power dissipation [1]. Failure analysis and its effects are major reliability concerns in electronic packaging. More accurate fatigue life prediction can be obtained after the consideration of all affecting loads on the electronic devices. In this study, an attempt is made to analyze 3 types of packages i.e. Wafer Level Chip Scale Package (WCSP), Quad Flat No-Lead (QFN) Package and 2-Die 3D TSV package. This study will be divided into 2 sections, one will focus on reliability and design optimization of 2D planar packages which includes only one die and other section includes discussion about 3D packages in which multiple dies are stacked on top of each other. The overall aim of this study is to analyze early failure mechanisms and mitigate problems faced by some assemblies. This includes material characterization, failure analysis, Finite Element Analysis, Design Optimization and proposes a better design to improve cycles to failure under reflow, thermal cycling and drop impact. Wafer Level Chip Scale packages are widely used packages nowadays, due to the low cost and smallest size. WCSP is a combination of Flip Chip packages and Chip Scale Packages. As the name suggests, IC packaging is formed at the wafer level in the wafer foundry. This is how WCSP is distinguished with other packages where packaging is done into 2 parts Wafer and Singulation of wafers into IC’s [2]. This is the reason manufacturer can save a lot of time during different stages of manufacturing and hence WCSP’s are less expensive. This study focuses on failure analysis of early failure in the packages and change in design parameters for improved solder joint reliability and mitigation of early failure. Further, the effect of different parameters like underfill, Cu pillars, Block of solder balls etc. are studied on the reliability of WCSP packages. Quad Flat No Lead Package is a Surface Mount Technology (SMT) also known as Micro Leadframe (MLF) and Small Outline No Leads (SON). This package is a near chip scale plastic encapsulated package made with a planar copper lead frame substrate [2]. In this study, a design optimization is performed to improve SJR for packages used with very thick PCB around 3.45mm. Different solder profile has been tested to observe the effect on SJR under thermal cycling. Furthermore, QFN is tested under drop test at various temperatures. This is attempting to analyze the impact of drop at a different temperature as electronic devices will not be necessary at OFF condition during the drop situation in real life. As the consumers demand more functions on their hand-held electronic devices, the need for more devices such as memory, CPU, and GPU in hand-held type footprints is increasing. Chip-stacking (3-D) is emerging as a powerful tool that satiates such IC package requirements [1]. A 3-D FPGA would overcome the interconnect limitations, resulting in greater silicon efficiency per function (number of used gates/total number of gates), faster signal/data throughput, and faster switching of the gate-level configuration. 3-D through-silicon-via (TSV) technology is being termed as the “next big thing” in the semiconductor arena and has the potential of revolutionizing the packaging industry but it has some inherent issues that need to be addressed before it could be implemented in the mainstream electronics industry. TSV fabrication process, thermal management of 3-D TSV packages, TSV joule heating, and chip package interaction (CPI), are some of the key issues in this technology. In this dissertation, the thermo-mechanical chip-package-interaction (CPI) analysis is carried out and a full field compact 3D modeling methodology has been leveraged to assess the mechanical integrity of a 2 die 3D TSV package during attachment to the substrate. This modeling methodology would provide damage predictions caused due to global and local CTE mismatch between the different package components. Mechanical interaction at the Si/TSV regions, back-end Cu/low-k stack and the inter-die µ-bumps during chip attachment is demonstrated in this study. Further, multivariable design optimization is carried out to improve the reliability of components under reflow and thermal loads. It is clear from this study that material used for mold and underfills plays important role in the reliability of the whole assembly.

Keywords

Solder Joint Reliability (SJR), Design optimization, FEA, WCSP, QFN, Chip-Package-Interaction (CPI), 3D TSV, Copper pumping, Underfill, Drop test, Reflow condition, Temperature Dependent Material Characterization

Disciplines

Aerospace Engineering | Engineering | Mechanical Engineering

Comments

Degree granted by The University of Texas at Arlington

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