Graduation Semester and Year
Summer 2025
Language
English
Document Type
Thesis
Degree Name
Master of Science in Materials Science and Engineering
Department
Materials Science and Engineering
First Advisor
Joseph Ngai
Second Advisor
Seong Jin Koh
Third Advisor
Choong-Un Kim
Abstract
This work explores the feasibility of integrating complex oxide devices on silicon using a CMOS-compatible, deposition-last approach. While previous demonstrations of this method have succeeded at larger scales, this study focuses on extending the process to microscale features, with lateral dimensions as small as two microns. The fabrication sequence begins with photolithographic patterning and reactive ion etching of the silicon substrate, followed by the deposition of a silicon nitride mask to delineate device regions. We then epitaxially grew SrTiO3 and La-doped SrTiO3 layers on top of the nitride mask via molecular beam epitaxy. Electrical transport measurements of the La:STO layer revealed semiconducting behavior as expected, suggesting that the intermediate material stack is operational. Future work will focus on YBCO deposition and, by extension, complete device characterization to assess Josephson behavior in the resulting junctions.
Keywords
Device fabrication, oxide heterostructures, heterointerfaces, microscale integration, oxide-semiconductor integration, perovskite heterostructures, step-edge dislocation, reactive ion etching, silicon nitride mask, deposition-last, pre-growth patterning, epitaxy, molecular beam epitaxy, oxide devices, oxide architectures, strontium titanate, silicon nitride, STO, SrTiO3, Si3N4
Disciplines
Condensed Matter Physics | Semiconductor and Optical Materials
License
This work is licensed under a Creative Commons Attribution 4.0 International License.
Recommended Citation
Brown, Jamal A., "Fabrication of Microscale Oxide Architectures on Silicon via a CMOS-Compatible, Deposition-Last Process" (2025). Material Science and Engineering Theses. 144.
https://mavmatrix.uta.edu/materialscieng_theses/144