Graduation Semester and Year
Summer 2026
Language
English
Document Type
Dissertation
Degree Name
Doctor of Philosophy in Materials Science and Engineering
Department
Materials Science and Engineering
First Advisor
Choong-Un Kim
Second Advisor
Dr. Ye Cao
Third Advisor
Dr. Seong Jin Koh
Fourth Advisor
Dr. Yaowu Hao
Fifth Advisor
Dr. Nancy L. Michael
Abstract
The continued downsizing of solder joints in modern electronic devices has made their structural and electrical reliability increasingly sensitive to coupled degradation mechanisms. As solder volume decreases, the joint no longer behaves as a large Sn reservoir. Instead, current crowding, Joule heating, Cu/Sn interdiffusion, intermetallic compound (IMC) growth, vacancy accumulation, thermal stress, and crack formation occur within the same confined region. Electromigration (EM) therefore becomes a critical reliability concern because it accelerates Cu dissolution, promotes polarity-dependent IMC growth, increases Kirkendall vacancy accumulation, raises local resistance, and can ultimately cause open-circuit failure.
To address this issue, we developed a fully coupled multiphysics phase field (PF) framework for Cu–Sn solder joints. The model integrates electrical current transport, Joule heat generation, transient temperature evolution, Cu/Sn interdiffusion, vacancy dynamics, Cu₆Sn₅/Cu₃Sn intermetallic compound (IMC) growth, stress evolution, stress assisted vacancy redistribution, electrical resistance evolution, and crack initiation and propagation wherever the local stress exceeds the interfacial fracture stress at metal/IMC interfaces or the fracture stress within the IMCs, all within a single computational framework.
The Cu–Sn system is important in electronic packaging because Cu₆Sn₅ and Cu₃Sn provide metallurgical bonding between solder and Cu metallization. However, these IMCs also control long-term reliability because they are brittle, more resistive than Sn, and closely linked to Kirkendall void formation. In the phase-field model, temperature-dependent diffusivities, thermodynamic driving forces, phase-dependent material properties, and solubility limits are used to reproduce realistic Cu₆Sn₅/Cu₃Sn morphology and thickness evolution. Vacancy transport includes ordinary diffusion, electromigration, thermomigration, and stress migration, allowing the model to identify vacancy flux divergence, supersaturation, void precursors, and early damage sites.
The electrical and thermal fields are directly coupled through Joule heating. Local current density defines the electron-wind driving force and current-crowding hot spots. Joule heating converts electrical localization into temperature rise, which increases diffusivity and accelerates vacancy migration. As IMCs grow and cracks form, the conducting path becomes narrower and more resistive, further increasing current crowding and heat generation. This positive feedback mechanism captures the accelerated damage evolution during the late stages of electromigration.
The structural module introduces thermal mismatch stress and stress-biased vacancy migration. Hydrostatic stress modifies the vacancy chemical potential and drives vacancy localization near tensile regions such as Cu/Cu₃Sn, Cu₃Sn/Cu₆Sn₅, and IMC/Sn interfaces. A tensile-stress-based damage criterion converts highly damaged regions into void-like or crack-like domains, allowing crack initiation and propagation to emerge from the coupled vacancy, stress, thermal, and electrical fields. The framework also shows that solder thickness strongly changes failure behavior. Thicker solder retains enough free Sn for IMC growth, creep relaxation, and stress redistribution, while thin solder loses this buffering ability as IMC growth consumes a large fraction of the joint. Once free Sn is depleted, failure becomes controlled by Joule heating, current crowding, thermal stress, and brittle IMC fracture.
Under extreme current stressing, solder interconnects can fail through mechanisms different from conventional EM voiding in the Sn-rich solder region. Testing of quad flat no-lead (QFN), pin-to-substrate, and lead-frame-to-substrate assemblies showed that damage can occur as cracking within the intermetallic compound layer. This behavior is attributed to the high-aspect-ratio solder geometry, which limits plastic deformation and stress relaxation in the Sn phase. As a result, the IMC layer is forced to accommodate EM-induced, reaction-induced, and thermal stresses.
Thermomechanical fatigue in thin Al and Cu interconnects under surge-current loading arises from repeated Joule heating and cooling, which generate cyclic thermal strain, stress, plastic deformation, and fatigue damage under dielectric and substrate constraint. Our experiments identified three power-dependent regimes: no measurable damage below a threshold, partial yielding with microscopic fatigue cracking and stress relaxation at intermediate power, and dielectric cracking, metal extrusion, and failure at high power. Narrow Al lines exhibited improved reliability because of their lower temperature rise per pulse and more effective heat dissipation. Cu interconnects showed similar fatigue behavior, although damascene confinement suppressed extrusion, shifting degradation toward localized Joule heating, stress accumulation, plastic deformation, work hardening, resistance evolution, and geometry-dependent failure.
Keywords
Electromigration, Reliability, Phase-field modeling, Intermetallic compounds, Interconnects, thermomechanical fatigue, Cu–Sn solder joints, Back End of Line (BEOL), Joule heating, Kirkendall voiding
Disciplines
Metallurgy | Semiconductor and Optical Materials
License
This work is licensed under a Creative Commons Attribution 4.0 International License.
Recommended Citation
Kumarasamy, harikrishnan, "Enabling Phase-Field Framework for Thermal Diffusion and Electromigration Studies in Lead-Free Cu–Sn Solder Joints" (2026). Material Science and Engineering Dissertations. 3.
https://mavmatrix.uta.edu/materialscieng_dissertations2/3
Comments
Acknowledgements to Dr. Choong-Un Kim for his guidance and support, the Semiconductor Research Corporation (SRC) for funding under Task IDs 3179.001 and 3303.001, and Texas Instruments, Dallas, for providing the samples used in this study.