Graduation Semester and Year
2015
Language
English
Document Type
Thesis
Degree Name
Master of Science in Electrical Engineering
Department
Electrical Engineering
First Advisor
Kamisetty R Rao
Abstract
High Efficiency Video Coding (HEVC) is the current state-of-art video codec which is widely being adopted by lot of users. It has close to 50% reduction in encoding time compared to its predecessor, H.264 or AVC (Advanced Video Coding) at the cost of increased complexity. Lot of research is going towards reducing the complexity of this codec, at the same time, maintaining the visual quality that it produces and maintaining the reduced encoding time from its predecessor. As an effort to decrease the encoding time further, there can be several approaches. Parallel processing is taking a dominant role in many places, especially in Graphics Processing Unit (GPU) and multi-cored processor based applications. Because of the ability of the parallel programming to utilize the multiple cores efficiently at the same time, in place of serial programming, this has been used in many applications which demand quicker completion. If areas that are parallelizable are identified in any codec (HEVC in this case), the encoding time can be drastically reduced by writing an efficient algorithm. In parallel programming, it is very important that the parallelized portion has the least amount of dependencies; otherwise it will lead to reverse effects of what is actually expected. Thus, the success lies in identifying the region of the codec that contributes more towards encoding time and that has least dependencies, and optimizing that portion of the codec. In this thesis, thorough analysis is done to identify the hot spots in the codec implementation, HM16.7, of High Efficiency Video Coding (HEVC) developed by the JCTVC team. This hotspot analysis is implemented using Intel’s most powerful tool, Intel® vTune™ Amplifier. The results of this hotspot analysis will be functions and loops that use most of the CPU time. Once this is identified, the respective function is targeted to be optimized using Parallel programming with OpenMP. Iterative runs are carried out on the modified code to check whether the code has been reasonably optimized. The final optimized code is tested for encoding videos using metrics such as PSNR (Peak Signal to Noise Ratio), R-D plot (Rate Distortion) and computational complexity in terms of encoding time. Through optimization of the HEVC HM16.7 encoder, there is an average reduction of ~24.7% to ~42.3% in encoding time with ~3.5 to 7% PSNR gain and ~1.6% to 4% bitrate increase.
Keywords
HEVC, Motion estimation, Parallel programming
Disciplines
Electrical and Computer Engineering | Engineering
License
This work is licensed under a Creative Commons Attribution-NonCommercial-Share Alike 4.0 International License.
Recommended Citation
Vijayaraghavan, Vasavee, "REDUCING THE ENCODING TIME OF MOTION ESTIMATION IN HEVC USING PARALLEL PROGRAMMING" (2015). Electrical Engineering Theses. 391.
https://mavmatrix.uta.edu/electricaleng_theses/391
Comments
Degree granted by The University of Texas at Arlington