Sharada Vajja

Graduation Semester and Year

2006

Language

English

Document Type

Thesis

Degree Name

Master of Science in Electrical Engineering

Department

Electrical Engineering

First Advisor

Alan W. Davis

Abstract

ABSTRACT Exponential increase of device sizes and complexity of ASICs mandate the need for design verification to meet timing specifications and functionality requirements. Verification techniques are broadly implemented in three categories viz., simulation, verification using commercial emulators and FPGA based prototyping. An Intel architecture based network processor, to be taped out in the near future, is being emulated on FPGA based platform. The basic blocks of the Network Processor, for instance, the Memory Controller Hub and I/O controller Hub were synthesized to be configured on FPGAs. The work involved synthesizing the design, partitioning it on multiple FPGAs and pin multiplexing of I/Os. Each sub unit of MCH and ICH were analyzed to resolve gated clocks not supported in FPGAs but widely used by ASIC designers for reducing power consumption. Synplicity's Certify tool is used for partitioning, pin multiplexing and for gated clock fixes. FPGA compatible block RAMs were generated with Xilinx Coregen. Design is being configured on Xilinx Virtex-4 FPGAs which provide high performance and high density boards for prototyping ASICs with millions of transistors. Xilinx ISE 8.1 is used for place and route of the design and to implement it for generate bit files burnt on PROMs to be configured on FPGA boards.

Disciplines

Electrical and Computer Engineering | Engineering

Comments

Degree granted by The University of Texas at Arlington

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