Graduation Semester and Year
2016
Language
English
Document Type
Thesis
Degree Name
Master of Science in Electrical Engineering
Department
Electrical Engineering
First Advisor
Taylor Johnson
Abstract
This document presents a design method and example for a time-triggered CAN (TTCAN) system which reduces latency, variability in transmission frequency, and increases data throughput relative to the traditional free-for-all CAN (FFACAN) transmission system. In addition to performance considerations for a TTCAN transmission scheme, this document also presents a simple method for measuring CPU usage on embedded systems that use either nested or non-nested interrupts. Systems that use non-nested interrupts may have their performance measured with a single GPIO pin; systems that use nested interrupts require one pin per interrupt service routine.
Keywords
Controller area networks, Time division multiple access, Formula SAE, CPU performance, CAN, TDMA, FSAE
Disciplines
Electrical and Computer Engineering | Engineering
License
This work is licensed under a Creative Commons Attribution-NonCommercial-Share Alike 4.0 International License.
Recommended Citation
Long, Randy Kyle, "Time-Triggered Controller Area Network Design for Formula SAE Racecars and Technique for Measuring CPU Usage on Systems with Nested and Non-Nested Interrupts" (2016). Electrical Engineering Theses. 138.
https://mavmatrix.uta.edu/electricaleng_theses/138
Comments
Degree granted by The University of Texas at Arlington