ORCID Identifier(s)

0000-0002-2690-2155

Graduation Semester and Year

Spring 2024

Language

English

Document Type

Dissertation

Degree Name

Doctor of Philosophy in Electrical Engineering

Department

Electrical Engineering

First Advisor

Prof. Weidong Zhou

Second Advisor

Prof. Robert Magnusson

Third Advisor

Prof. Michael Vasilyev

Abstract

Photonic Crystal Surface Emitting Laser (PCSEL) is the promising third generation semiconductor laser technology as it addresses the challenges of the conventional semiconductor lasers (EEL/VCSEL) by providing single mode high power output with good beam quality (thus high brightness). The large area in plane coupling resulting from the multiple Bragg’s diffraction conditions in the periodic 2D photonic crystal cavities in the lasing cladding region leads to single mode operation over very large area. By model design engineering, such in plane lasing cavity can leak the light out of the plane, which result in surface emission. The ability to scale the photonic crystal cavity size to several hundred micrometers, or even millimeter sizes yet maintaining single mode operation at high power (theoretically predicted up to kW) is very encouraging as they could replace the bulkier and less efficient conventional laser such as gas lasers, solid state lasers, fiber lasers, etc. In addition, the possibility of beam steering at high speed and high power operations are equally important areas of PCSELs.

We report simulation results followed by experimental demonstration to show the impact of p contact pad size on improving the PCSEL performance. This is based on the idea of maximizing the overlapping factor with fundamental mode while suppressing higher order mode lasing. We achieved watt level PCSELs from 250 µm × 250 µm photonic crystal cavity size with dominant single spectrum at 1040 nm. A single dominant near gaussian spatial beam profile was realized from electrically biased PCSEL up to the injection current several times the lasing threshold. Flip chip bonding process was developed to facilitate quick and fast testing. An effort to scale up the cavity size to fabricate higher power PCSELs and corresponding device performance is also presented.

Even though it possesses great potential to scale up for higher output power yet maintaining single mode operation, there are some design challenges such as decreasing gain threshold difference, thermal issue, and carrier non uniformity. To address these issues, we designed and demonstrated an innovative way to fabricate PCSEL arrays so that multiple PCSELs of reasonable size arranged in an array can emit higher power with good beam quality. The evanescent modes leaking laterally from the adjacent PCSELs is used to realize the coherent compact PCSEL arrays. Heterolattice photonic crystal design is employed to create band discontinuity in the core and clad region. The cavity Q factor is optimized by controlling the cladding region. Circular airhole photonic crystal cavity patterned in GaAs were arranged in 2×2 arrays separated by coupling region of length 17 µm. These arrays after regrowth were etched down following p metal deposition to electrically isolate individual devices. The measured single dominant spectral and spatial beam profile for PCSEL array is similar to single PCSEL while the output power for PCSEL array was scaled up proportional to the PC cavity area.

PCSELs can achieve higher power with reasonable speed of few GHz. In this dissertation we report the experimental demonstration of 200 µm × 200 µm PCSELs with few GHz speed and watt level output power. The demonstrated 4.78 GHZ bandwidth was at 1A injection current. We expect even better performance at higher current injection after better thermal management of PCSEL devices. To assess the power-speed performances, we plot the product of power and bandwidth as figure-of-merit (FOM) and obtained a value of 350 mA⋅GHz whereas the corresponding value for VCSEL is 300 mA⋅GHz. This suggests the PCSEL as a better candidate for high speed and high power applications. The size of the active region is an important factor to determine the speed of the PCSEL so we scaled down the devices to realize higher speed. The smaller PCSELs up to 50 µm of cavity has been demonstrated to explore the speed and corresponding power.

Thermal management is one of the critical challenges for such smaller PCSEL devices. Especially when we bias the devices with higher injection current density, more heat would be generated in the PCSELs creating issues related to output power, spectral properties, and many other undesired thermo-optical effects. We simulated potential structures in COMSOL Multiphysics utilizing SiC and diamond as heat sink and theoretically observed significant reduction on the device temperature. Diamond sub mount is the most effective in thermal management as it reduces the device temperature by more than 50%. Another approach for thermal management and device packaging has also been investigated. We diced the PCSEL chip to get individual PCSEL devices and bonded to sub mount which helps for thermal dissipation and individual electrical biasing. A comprehensive report on the device performance in this new device architecture is under progress.

Keywords

Photonic Crystal Surface Emitting Lasers, PCSEL, High Speed PCSEL, High Power PCSEL, PCSEL Array, Thermal Management

Disciplines

Electrical and Electronics | Electromagnetics and Photonics | Electronic Devices and Semiconductor Manufacturing | Nanotechnology Fabrication

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