Tanvir Ahmed

Graduation Semester and Year




Document Type


Degree Name

Doctor of Philosophy in Electrical Engineering


Electrical Engineering

First Advisor

Zeynep Celik-Butler


Electrical stressing mechanisms are responsible for the generation of stress-induced gate SiO2 defects, in addition to the presence of process-induced oxide traps, in MOSFETs. Random telegraph signal (RTS) can be utilized as a tool to characterize these defects. Channel hot carrier (CHC) stressing is reported to result in the worst degradation in pMOSFETs. However, the effects of CHC on RTS for pMOSFETs are under-reported. The main objective of this work is to investigate the impact of the CHC stressing on pMOSFETs by analyzing RTS. For this reason, the effects of CHC stressing on different RTS parameters are examined. Additionally, responsible defect sites are identified. At first, CHC stressing is conducted for up to 2000 seconds with variable time intervals of 5 seconds to 200 seconds under room temperature. Then, different RTS parameters are inspected to study the impact of CHC stressing. The investigated RTS parameters are average carrier capture and emission times by the trap, trap position, trap energy level with respect to the oxide valence band edge, capture cross-section, RTS amplitude, and screened scattering coefficients. CHC stressing does not impact the position of the trap and the trap energy level with respect to the oxide valence band edge. The decrease of relaxation energy is considered to be responsible for the change in average capture time and capture cross-section with stressing for the stress-induced traps. However, further investigations are required which would focus on variable temperature measurements. The generated fixed positive oxide charges result in additional charge screening on the traps with stressing. Therefore, the Coulomb screened scattering coefficient decreases. As a result, the amount of mobility fluctuations is lowered, and we observe an increase in RTS amplitude with stressing. The novelty of this work lies in the fact that the two-dimensional mobility fluctuations model is implemented for the very first time to theoretically determine the screened scattering coefficients under CHC stressing in pMOSFETs. Later, these theoretically determined screened scattering coefficients are compared with the measured ones. Moreover, detailed studies of the thermal activation process and structural relaxation energies are required to identify the defect centers under CHC stressing. Therefore, performing the variable temperature RTS measurements is necessary. To fully characterize the defects, variable temperature RTS measurements are conducted from room temperature down to 215 K. CHC stressing is performed for up to 1200 seconds. Additional RTS trap parameters such as capture activation energy, emission activation energy, relaxation energy, change in enthalpy, and change in entropy are determined. Faster capture times are exhibited by the stress-induced traps, which result from the larger trap capture cross-sections. A pronounced difference is observed in the change of entropy among the process- and stress-induced traps upon hole emission from the defect site to the Si valence band. This points to the possibility of a different structural defect being responsible behind the stress-induced traps than the native ones. Two different types of defects, D-III Si and hydrogen bridge are identified as the trapping center in SiO2 for the pMOSFETs under CHC stressing. Like RTS, flicker (1/f) noise has also been a prominent source of noise in MOSFETs. Our goal is to find ways to passivate the traps and thereby minimize the amount of 1/f noise. 1/f noise PSD measurements are carried on nMOSFETs from three different wafers. Then the current noise PSD data are normalized with respect to the channel width, length, and oxide layer thickness. Later, 1/f noise PSD data are curve fitted to the unified numbers and mobility fluctuations (UNMF) model to determine the trap density and the screened scattering coefficients. The normalized 1/f noise data are correlated with the fabrication steps across the wafers. By incorporating necessary changes in the fabrication steps, 1/f noise can be minimized.


Random telegraph signal (RTS), Channel hot carrier (CHC) stress, Hydrogen bridge oxide defects, Disassociated III-Si defects, Flicker (1/f) noise


Electrical and Computer Engineering | Engineering


Degree granted by The University of Texas at Arlington