Graduation Semester and Year




Document Type


Degree Name

Doctor of Philosophy in Electrical Engineering


Electrical Engineering

First Advisor

Zeynep Celik-Butler


The focus of this work is to study the noise and degradation in advanced high and low voltage analog Metal Oxide Semiconductor Field Effect Transistors (MOSFET). Medium and high voltage transistors, especially lateral double diffused MOS (LDMOS) FETs have numerous practical applications. Although the LDMOS concept dates back some years, importance of low-frequency noise (also known as 1/f noise) characteristics of these devices have attracted attention only recently, due to some major reliability concerns. As an example, 1/f noise can cause a severe impact in System-on-Chip (SOC) applications when the LDMOS transistor is coupled with other devices or circuits through the substrate or in oscillators, gate drives and analog voltage converters. Therefore, study of degradation and lifetime for these advanced power devices is vital from semiconductor industry point of view. Here, the DC stress induced degradation characteristics of differently processes LDMOS are studied along with the noise performance. It is illustrated in this work that modeling the DC degradation alone cannot fully explain the physical mechanisms for LDMOS degradation. Hence, 1/f noise was utilized as a non-destructive characterization tool for quantitatively evaluate the device reliability and degradation after they were subjected to worst stress induced degradation condition. A correlation has been established between low frequency noise and DC stress induced degradation. From that, a simple but well-defined approach has been delineated to separate the individual resistance and noise components in different regions of these devices. Effect of extended drain drift region scaling on 1/f noise performance is depicted for different foundry-fabricated devices. An early lifetime prediction method for LDMOS is also reported here using 1/f noise measurement. This work reports the first ever physics-based 1/f noise model for LDMOS devices, and demonstrates that the developed model can correctly predict the experimentally observed noise behavior in the linear region of operation in fresh devices as well as in stressed devices. The model is based upon the correlated carrier number and mobility fluctuation theory known as the unified noise model, but has been modified to account for the fluctuations in the extended drain as well as the channel. Unlike the unified 1/f noise model, non-uniform trap distribution has been taken into account with respect to the position in the gate oxide and the band-gap energy. On the other hand, continuous downscaling of advanced submicron area low voltage analog MOSFETs requires rigorous in-depth study of the gate-oxide reliability. While 1/f noise study is promising in case of relatively large area transistors, Random telegraph signal (RTS) noise is a potential non-destructive characterization technique for assessing semiconductor device reliability in small area transistors. This is because, with RTS noise study, each individual physical defect can be isolated, and trap properties can be described both quantitatively and qualitatively. In this dissertation, multiple level RTS have been studied in submicron NMOS transistors at room temperature. Two different types of active traps- donor and acceptor, responsible for RTS generation, have been identified in the same NMOS transistors. A numerical computation method has been developed to separate fluctuations due to each trap, and to calculate the mean capture and emission time, trap energy, capture cross-section and the distance into the oxide.


Electrical and Computer Engineering | Engineering


Degree granted by The University of Texas at Arlington