Graduation Semester and Year
Fall 2025
Language
English
Document Type
Thesis
Degree Name
Master of Science in Computer Engineering
Department
Computer Science and Engineering
First Advisor
Bill Carroll
Second Advisor
David Levine
Third Advisor
Mohammad Islam
Abstract
Large language models like ChatGPT are transforming the way engineers design digital systems. This thesis explores how ChatGPT, when guided by structured, code-focused prompts, can automatically generate synthesizable SystemVerilog modules and comprehensive testbenches that integrate seamlessly with professional simulation tools.
To evaluate this capability, I developed a fully automated pipeline that leverages the ChatGPT API (gpt-4-turbo) to create both the SystemVerilog code and its testbench. These components are saved on a Windows system and compiled, simulated, and analyzed using QuestaSim, driven by Python-generated .do scripts. This approach eliminates manual copy-paste errors, accelerates design iterations, and ensures consistent simulation workflows.
Keywords
SystemVerilog, LLM in HW, HDL, HDL generation
Disciplines
Digital Circuits | Hardware Systems
License
This work is licensed under a Creative Commons Attribution 4.0 International License.
Recommended Citation
Ahmed, Khaled H., "USING CHATGPT TO GENERATE AND VALIDATE SYSTEMVERILOG CODE" (2025). Computer Science and Engineering Theses. 535.
https://mavmatrix.uta.edu/cse_theses/535