Parinda Patel

Graduation Semester and Year




Document Type


Degree Name

Master of Science in Aerospace Engineering


Mechanical and Aerospace Engineering

First Advisor

Dereje Agonafer


In this advanced technological era, all electronic equipments tend to be light in weight, and have high performance with low power consumption and low prices. Gain in both performance and cost via Moore's law is starting becoming difficult post 28nm technology node. Three dimensional chips staking with TSV technology has gained momentum to meet such requirements of significant miniaturization and power reduction which result in increased performance. Vertically interconnected TSVs provide the shorter effective electrical interconnect path, resulting in reduced signal latency between strata and greater signal bandwidth. Moreover, TSVs offer high density integration, increased number of input/output terminals and reduction in power consumption by cutting out the power losses which enables the elimination of heating. However, the unique issues related to yield and reliability of critical areas in TSV based 3D ICs need to be evaluated. In this research 3D chip is subjected to thermal loading, heating thermal cycling. Under the loading, the critical area of concern is Si & Cu interface. This research involves the investigation of the interfacial cracking of Si & Cu, elastic strain energy developed at the interface under thermal cycling. The high coefficient of thermal expansion mismatch between Si & Cu causes the pressing issues related to interfacial de-lamination. When the 3D IC is thermal cycled the different materials in the contact tend to expand/contract according to their CTE's. The contact material (at the interface) is (usually) the weakest point in the model so it is expected to absorb the stresses of thermal mismatch by yielding in creep. The amount of creep an interface can endure is limited, and then it will begin to crack. Structural integrity of Si & Cu was developed by stress intensity factor, and this developed stress intensity factor was compared with the fracture toughness of Si. FEA was used to examine the mechanical effects by doing a series of stress analysis under low/high thermal cycling, which take into account the magnitude of thermal load, TSV geometry, etc. Large stresses were developed at the interfaces result in interface failures. Interfacial de-lamination of TSVs was encountered mainly driven by a shear stress concentration for the heating conditions and mixed mode fracture was occurred under cooling conditions at the interface. The parameters affecting the crack growth at the interface have been investigated.


Aerospace Engineering | Engineering | Mechanical Engineering


Degree granted by The University of Texas at Arlington