Graduation Semester and Year




Document Type


Degree Name

Master of Science in Mechanical Engineering


Mechanical and Aerospace Engineering

First Advisor

Dereje Agonafer


Since the introduction of Chip Scale Packages (CSP’s) in the early 2000s, they have become one of the biggest packaging trends in recent history. There are currently over 50 different types of CSP’s available throughout the industry and the numbers are increasing almost daily. Wafer Level Chip Scale Package’s (WCSP) is kind of CSP’s used widely due to its small form factor which offers efficient use of limited space and miniaturization of the electronic device. On the other hand, small form factor typically incurs greater initial cost in product design and development. In an electronic device, it is equally important to design a device with greater mechanical stability, with electrical stability as well. In this study, I am going to optimize the design of WCSP to enhance the thermo-mechanical reliability of the package by studying the effect of DNP. Further, the attempt has been made to study the effect of a void on BLR and SJR in the critical solder joint during thermal cycling and reflow condition. For this study PCB of 1 mm was leveraged. Thermo-Mechanical Analyzer (TMA), Dynamic Mechanical Analyzer (DMA) and, Oven were used to characterize material properties. PCB cross-sectioning was done using a cutter and Optical Microscopy was used to study voids and layer by layer composition of PCB. ANSYS Workbench 18.0 was leveraged to model 3D CAD of the quarter geometry of PCB and it was used to do the computational study.


WCSP, Reliability, Void, DNP


Aerospace Engineering | Engineering | Mechanical Engineering


Degree granted by The University of Texas at Arlington