ORCID Identifier(s)

0009-0002-7056-8606

Graduation Semester and Year

2023

Language

English

Document Type

Thesis

Degree Name

Master of Science in Computer Science

Department

Computer Science and Engineering

First Advisor

Bill D Carroll

Abstract

In today’s day and age of arithmetic, Floating Point Arithmetic is by far the most industry sanctioned way of approximating real number arithmetic for making numerical calculations on all computers used by industries on an everyday basis. In the year 1985, IEEE 754 standard was established that defined a single universal standard for all different arithmetic formats [1]. Before this, for a long period each computer had a different arithmetic format and size for bases, significand, and exponents. This format allowed industries all around the world to compute floating point arithmetic in a universal way and facilitated open communication between all worlds. The first objective of this project is implementing a single precision binary floating point processing unit in accordance with the IEEE 754 standard using Verilog hardware description language and writing test benches to run ModelSim simulations for testing. The second objective of this project is to convert the implementation of the single precision floating point unit into an education model. The purpose of this education model will be to educate future Digital Logic & Design students in the field of floating-point processing and provide them a roadmap to build their own floating-point processor using a series of lab assignments.

Keywords

Floating point unit, FPGA, Verilog, System verilog, Hardware architecture, Wallace multiplier

Disciplines

Computer Sciences | Physical Sciences and Mathematics

Comments

Degree granted by The University of Texas at Arlington

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