ORCID Identifier(s)

ORCID 0000-0002-0926-2838

Graduation Semester and Year

Spring 2025

Language

English

Document Type

Dissertation

Degree Name

Doctor of Philosophy in Electrical Engineering

Department

Electrical Engineering

First Advisor

Chenyun Pan

Abstract

As technology nodes continue to scale down, traditional copper (Cu) interconnects with repeater insertion face significant challenges, e.g., increased resistance and delay, higher power consumption, and reduced reliability. It is no longer sufficient to compensate for the overhead of interconnects solely by enhancing transistor or logic gate performance. In fact, at sub-2nm technology nodes, the significance of interconnect performance has surpassed the logic gates counterpart, making interconnects the primary bottleneck limiting the overall performance of semiconductor circuits. To address these limitations, emerging interconnect solutions are required to enhance performance, power efficiency, and area utilization (PPA).

The proposed Cacti++ framework is an advanced solution designed to overcome the limitations of system-level design verification and simulation in the early stages of technology development. The Cacti++ executable tool has been developed in C++ and makefile on the Linux platform. It enables rapid evaluation of PPA of memory systems for advanced technology nodes using PDK from IMEC, ranging from validated 5- to 14-Å-compatible technologies, etc. The Cacti++ framework facilitates the co-design and co-optimization of interconnect technologies and memory architectures by seamlessly integrating multiple levels—from fundamental technology nodes, transistors, and devices to circuits, interconnects, subarrays, arrays, memory systems, and high-level software/algorithm workloads—bridging the gap between hardware and software. This framework offers valuable guidance for the development of CAD and EDA tools, process technology advancements, interconnect and circuit design optimization, as well as modeling and comprehensive optimization for co-design analysis across technology nodes, interconnects, circuits, memory systems, and artificial intelligence (AI) algorithms.

Graphene has emerged as a promising alternative to Cu interconnects due to its superior electrical and thermal properties. This dissertation explores the potential of graphene-based interconnects for generic Very Large-Scale Integration (VLSI) systems and investigates their applicability in memory arrays. In addition, a comprehensive analysis is conducted to evaluate the impact of the proposed interconnect designs on the PPA of the cache memory system in the developed Cacti++ framework based on state-of-the-art technology nodes. The graphene-based approach is evaluated, highlighting its potential to reduce the delay and lower power consumption.

Furthermore, a novel hybrid interconnect design leveraging differential transmission lines (DTL) is proposed to further improve PPA by comparing DTL with traditional repeater insertion by the proposed Cacti++ framework based on rigorous industry standard simulation. The hybrid DTL approach is analyzed for memory applications, demonstrating its potential to mitigate signal degradation and reduce power consumption in memory systems.

Through extensive modeling, simulation, and comparative analysis, this research provides valuable insights into the feasibility of graphene-based and DTL interconnects as next-generation interconnect solutions. The findings contribute to advancing energy-efficient and scalable interconnect architectures for future VLSI logic and memory applications.

Chapter 2 primarily describes interconnect modeling methodologies, including the graphene heterogeneous interconnect model, the equation-based repeater interconnect model, as well as the DTL model and the conventional interconnect with repeater insertion model based on industrial-standard simulations.

In Chapter 3, a comprehensive modeling and optimization framework is developed to analyze and benchmark the performance of generic wires utilizing ballistic materials. Key device-/material-level parameters, e.g., MFP, channel density, and contact resistance, are examined to optimize chip-level throughput. At the system level, two design strategies are proposed, exploring the replacement of traditional Cu wires with ballistic materials at different interconnect layers.

For Chapter 4, a comprehensive analysis is performed to assess the impact of the proposed graphene-based interconnect with innovative designs on the PPA of the cache memory system within the enhanced Cacti++ framework. The graphene-based approach is systematically analyzed, demonstrating its potential to reduce delay and lower power consumption at the system level under both hardware and software conditions.

In Chapter 5, an exploration is conducted to evaluate the impact of the proposed DTL interconnect with innovative designs on the PPA within the Cacti++ framework. This evaluation, based on industry-standard simulations, compares the hybrid DTL approach with traditional repeater insertion interconnects. The hybrid DTL design is systematically examined, highlighting its potential to reduce power consumption with robust signal integrity and stable voltage for the SRAM cache memory systems under algorithm workloads.

Chapter 6 summarizes the PPA optimization in generic VLSI systems and memory arrays based on emerging interconnect designs/technologies and presents future work on modeling and optimization from the device level to the system level.

Keywords

Interconnect, SRAM, Benchmark, DTL, Workload, Center-pin access, E-Tree, Mean free path, Design/technology co-optimization, Graphene.

Disciplines

Computer-Aided Engineering and Design | Computer and Systems Architecture | Data Storage Systems | Digital Circuits | Electrical and Electronics | Electronic Devices and Semiconductor Manufacturing | Hardware Systems | Nanoscience and Nanotechnology | Nanotechnology Fabrication | Other Computer Engineering | Other Computer Sciences | Other Electrical and Computer Engineering | Programming Languages and Compilers | Software Engineering | VLSI and Circuits, Embedded and Hardware Systems

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